This part is a kind of semiconductor called 74LS73.

Function of this product has DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP.

Manufacturers : Motorola

Image and pinout :

Some of the text within the PDF file :

SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 Q 13 (8) Q 12 (9) 1 CLEAR 2 (6) K 3 (10) 1 (15) CLOCK (CP) J 14 (7) 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 OR [ ... ]

74LS73 PDF Datasheet Download